By Jayant Narlikar
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It is not realistic to add a body contact to FD-SOI, since there is no guarantee of a body region being available under most operating conditions. 29]. This may vary typically by approximately 8% faster or slower than a nominal state. As a minimum, test routines are required to force the body voltages to the extreme delays. This approach however, can cause overcompensation, resulting in excessive margin. Minimization of design margin is discussed in chapter 6. Variations in the floating body voltage of PD-SOI MOS transistors causes an uncertainty in the gate-source threshold voltage.
Digest, 1998, pp. 403 - 406. 37] D. Flandre, et. , "Fully-Depleted-SOI cMOS technology for lowvoltage low-power digital/analog/microwave circuits", Analog Integrated Circuits and Signal Processing. New York: Kluwer, 1998. 38] J-P. Eggermont, et. , "Potential and Modeling of SOI cMOS Operational Transconductance Amplifiers for Applications up to 1 Ghz" IEEE Journal of Solid State Circuits, Vol. 33, No. 4, April 1998, pp 640 643. 39] S. M. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, New York.
It is also necessary to correct for self-heating effects when making DC SOI current measurements. For this type of measurement a typical device shows selfheating degradation in Ids values of between 3 and 10%. 63]. g. 0 (chapter 4) include self-heating components, and it is considered essential to include self-heating in the modeling of analog circuits. 65]. 1 Self Heating from elsewhere on the same chip Digital Circuits Bulk digital CMOS design rarely needs to consider heating effects. With higher current densities of modern processes and the poor thermal 38 Chapter 2: SOI Materials conductivity of the buried oxide layer, it is not necessarily the case that thermal effects can still be ignored.
A Journey Through The Universe by Jayant Narlikar